For inter-die data transfers, a synchronous system is often used. To guard against timing failure from the process, voltage, and temperature (PVT) variations between the two dies, various factors including, for example, inter-die compensation, clock skew, and uncertainty, affect the timing budget for synchronous circuits. As a result, the crossing frequency for the inter-die data transfer is limited. On the other hand, existing asynchronous die crossing systems usually use additional crossing wires and has a low throughput to provide asynchronous clock domain crossings. For example, a reliable clock domain crossing for a bus usually uses a handshake that reduces throughput. For further example, an asynchronous first-in first out buffer (FIFO) used for clock crossing may need more wires for addressing when that asynchronous FIFO is divided into two dies. Such asynchronous die crossing systems may also require a data width that is fixed in advance.
Accordingly, it would be desirable and useful to provide an improved inter-die data transfer system.